1. Field of the Invention
The present invention relates to integrated circuits having a memory array and the capability for testing the memory.
2. Description of the Prior Art
The use of memory arrays integrated with logic circuitry, referred to as "embedded memories" or "application specific memories", results in a memory array that is more difficult to test than a conventional discrete memory integrated circuit (IC). This is due largely to the fact that the access to the memory array itself is limited. That is, the input/output terminals are usually devoted to the logic functions that the IC is intended to perform, and the memory array itself is not directly accessible to the user. Therefore, the testing is usually limited to storing and retrieving data through the intervening logic circuitry, which may not provide a complete test. Furthermore, even if any error is detected, it is frequently not clear whether the logic circuitry or the memory array is at fault. That information is very useful when debugging new designs, and for monitoring processing conditions during production, for example.
One technique for testing the memory array itself is to provide test pads on the integrated circuit that are devoted to the memory array. However, that results in a substantial increase in the integrated circuit area, which is not usually economically feasible. Furthermore, the time required for testing a large memory array is substantial. In addition, the package test may then not be as complete as the wafer test, reducing the ability to detect faults at the package test. Another known technique is to include on the integrated circuit a test generator that generates a known sequence of test bits that are written into the array. The test bits are then read from the array, and compared with the known pattern in a signature recognition circuit. However, the prior art techniques have not yielded as complete a test as is desired, since the signatures used have typically not simulated worst-case conditions very closely.
When the test circuitry is included on the same IC as the memory, the test circuitry should also be tested. However, this is typically very difficult using prior art test techniques. Finally, the custom logic designs of the prior art signature generation and recognition circuitry are not very regular. Hence, they are difficult to partition when computer-aided design (CAD) techniques are used, especially the CAD techniques that group the circuitry into blocks.